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5-A H-Bridge for DC-Motor Applications
Preliminary Data Overview Features * * * * * * * * * * * * Delivers up to 5 A continuous 6 A peak current Optimized for DC motor management applications Operates at supply voltages up to 40 V Very low RDS ON; typ. 200 m @ 25 C per switch Output full short circuit protected Overtemperature protection with hysteresis and diagnosis Short circuit and open load diagnosis with open drain error flag Undervoltage lockout CMOS/TTL compatible inputs with hysteresis No crossover current Internal freewheeling diodes Wide temperature range; - 40 C < Tj < 150 C Ordering Code Package Q67000-A9283 P-TO220-7-11 Q67006-A9237 P-DSO-20-10 Q67006-A9325 P-TO263-7-1 Q67000-A9324 P-TO220-7-12 P-TO263-7-1
TLE 5205-2
P-TO220-7-11
P-DSO-20-10
Type TLE 5205-2 TLE 5205-2GP TLE 5205-2G TLE 5205-2S
Description The TLE 5205-2 is an integrated power H-bridge with P-TO220-7-12 DMOS output stages for driving DC-Motors. The part is built using the SIEMENS multi-technology process SPT(R) which allows bipolar and CMOS control circuitry plus DMOS power devices to exist on the same monolithic structure. Operation modes forward (cw), reverse (ccw), brake and high impedance are invoked from just two control pins with TTL/CMOS compatible levels. The combination of an extremely low RDS ON and the use of a power IC package with low thermal resistance and high thermal capacity helps to minimize system power dissipation. A blocking capacitor at the supply voltage is the only external circuitry due to the integrated freewheeling diodes.
Semiconductor Group 1 1998-02-01
TLE 5205-2
TLE 5205-2
TLE 5205-2GP
1
2
3
4
5
6
7
GND N.C. N.C. N.C. N.C. VS Q1 EF 1 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
AEP01680
GND N.C. N.C. N.C. N.C. VS Q2 N.C. 2 GND
TLE 5205-2S
EF OUT1 GND IN1 IN2
VS
OUT2
AEP01990
TLE 5205-2G
1
23
456
7
12
3
4
5
67
OUT1 IN1 IN2 OUT2 EF GND V S
AEP01991
OUT1 EF
IN1
IN2
OUT2
GND
VS
AEP02513
Figure 1
Pin Configuration (top view)
Semiconductor Group
2
1998-02-01
TLE 5205-2
Pin Definitions and Functions Pin No. P-TO220 1 2 3 4 5 6 7 - Pin No. P-DSO 7 8 9 1, 10, 11, 20 12 6, 15 14 Symbol OUT1 EF IN1 GND IN2 Function Output of channel 1; Short-circuit protected; integrated freewheeling diodes for inductive loads. Error flag; TTL/CMOS compatible output for error detection; (open drain) Control input 1; TTL/CMOS compatible Ground; internally connected to tab Control input 2; TTL/CMOS compatible Supply voltage; block to GND Output of channel 2; Short-circuit protected; integrated freewheeling diodes for inductive loads. Not connected
VS
OUT2
2, 3, 4, 5, N.C. 16, 17, 18, 19
Semiconductor Group
3
1998-02-01
TLE 5205-2
VS
EF 2 Error Flag
Diagnosis and Protection Circuit 1
6
IN1
3
1 0 0 1 1
IN 2
OUT 12
1
OUT1
IN2
5
010 101 000 1ZZ
7
OUT2
Diagnosis and Protection Circuit 2
4 GND
AEB02394
Figure 2
Block Diagram
Circuit Description Input Circuit The control inputs consist of TTL/CMOS-compatible schmitt-triggers with hysteresis. Buffer amplifiers are driven by this stages. Output Stages The output stages consist of a DMOS H-bridge. Integrated circuits protect the outputs against short-circuit to ground and to the supply voltage. Positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes. A monitoring circuit for each output transistor detects whether the particular transitor is active and in this case prevents the corresponding source transistor (sink transistor) from conducting in sink operation (source operation). Therefore no crossover currents can occur.
Semiconductor Group
4
1998-02-01
TLE 5205-2
Input Logic Truth Table Functional Truth Table IN1 L L H H IN2 L H L H OUT1 H L L Z OUT2 L H L Z Comments Motor turns clockwise Motor turns counterclockwise Brake; both low side transistors turned-ON Open circuit detection
Notes for Output Stage Symbol L H Z Value Low side transistor is turned-ON High side transistor is turned-OFF High side transistor is turned-ON Low side transistor is turned-OFF High side transistor is turned-OFF Low side transistor is turned-OFF
Monitoring Functions Undervoltage lockout (UVLO): When VS reaches the switch on voltage VS ON the IC becomes active with a hysteresis. All output transistors are switched off if the supply voltage VS drops below the switch off value VS OFF. Protective Function Various errors like short-circuit to + VS, ground or across the load are detected. All faults result in turn-OFF of the output stages after a delay of 50 s and setting of the error flag EF to ground. Changing the inputs resets the error flag. a. Output Shorted to Ground Detection If a high side transistor is switched on and its output is shorted to ground, the output current is internally limited. After a delay of 50 s all outputs will be switched-OFF and the error flag is set. b. Output Shorted to + VS Detection If a low side transistor is switched on and its output is shorted to the supply voltage, the output current is internally limited. After a delay of 50 s all outputs will be switched-OFF and the error flag is set.
Semiconductor Group
5
1998-02-01
TLE 5205-2
c. Overload Detection An internal circuit detects if the current through the low side transistor exceeds the trippoint ISDL. In this case all outputs are turned off after 50 s and the error flag is set. d. Overtemperature Protection At a junction temperature higher than 150 C the thermal shutdown turns-OFF, all four output stages commonly and the error flag is set with a delay. e. Open Load Detection The output Q1 has a 10 k pull-up resistor and the output Q2 has a 10 k pull-down resistor. If E1 and E2 are high, all output power stages are turned-OFF. In case of no load between Q1 and Q2 the output voltage Q1 is VS and Q2 is ground. This state will be detected by two comparators and an error flag will be set after a delay time of 50 s. Changing the inputs resets the error flip flop.
V EH =
Pull UP 10 k EF = Pull Down 10 k
V EL
&
50 s
RS FF
AES02395
Figure 3
Simplified Schematic for Open Load Detection
Semiconductor Group
6
1998-02-01
TLE 5205-2
Diagnosis Various errors as listed in the table "Diagnosis" are detected. Short circuits and overload result in turning off the output stages after a delay (tdoff for short circuit and tdoc for open circuit) and setting the error flag simultaneously [EF = L]. Changing the inputs to a state where the fault is not detectable resets the error flag (input toggling) with the exception of short circuit from OUT1 to OUT2 (load short circuit).
Flag Open circuit between OUT1 and OUT2 IN1 IN2 OUT1 OUT2 EF Remarks 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 H L L Z L H L Z 1 1 1 0 0 0 1 1 0 1 1 1 1 0 1 1 1 0 0 1 0 1 0 1 0 0 0 0 Not detectable Not detectable Not detectable Nr. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 = No error 0 = Error
Short circuit from OUT1 to OUT2
VS/2 VS/2
L Z GND GND GND GND H L L L
VS/2 VS/2
L Z L H L L GND GND GND GND L H H H
Not detectable Not detectable Not detectable Not detectable Not detectable Not detectable Not detectable Not detectable Not detectable
Short circuit from OUT1 to GND
Short circuit from OUT2 to GND
Short circuit from OUT1 to VS
VS VS VS VS
H L H H Z Z Z Z
Not detectable Not detectable Not detectable
Short circuit from OUT2 to VS
VS VS VS VS
Z Z Z Z
Overtemperature or undervoltage
IN:
EF: 0 = Logic LOW OUT: Z = Output in tristate condition 1 = Logic HIGH = VS /2 due to internal Pull-up/down resistors L = Output in sink condition H = Output in source condition
Semiconductor Group
7
1998-02-01
TLE 5205-2
Electrical Characteristics Absolute Maximum Ratings - 40 C < Tj < 150 C Parameter Symbol Limit Values min. Voltages Supply voltage Logic input voltage Diagnostics output voltage max. Unit Remarks
VS VIN1, 2 VEF
- 0.3 -1 - 0.3 - 0.3
40 40 7 7
V V V V
-
t < 0.5 s; IS > - 5 A 0 V < VS < 40 V
-
Currents of DMOS-Transistors and freewheeling diodes Output current (cont.) Output current (peak) Output current (peak)
IOUT1, 2 IOUT1, 2 IOUT1, 2
-5 -6 -
5 6 -
A A A
-
tp < 100 ms; T = 1 s tp < 50 s; T = 1 s;
internally limitted; see overcurrent
Temperatures Junction temperature Storage temperature Thermal Resistances Junction case Junction ambient Junction case Junction ambient
Tj Tstg
- 40 - 50
150 150
C C
- -
RthjC RthjA RthjC RthjA
- - - - -
3 65 75 5 50
K/W K/W K/W K/W K/W
P-TO220-7-11/12, P-TO263-7-1 P-TO220-7-11/12 P-TO263-7-1 P-DSO-20-10 P-DSO-20-10
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
Semiconductor Group
8
1998-02-01
TLE 5205-2
Operating Range Parameter Supply voltage Supply voltage increasing Supply voltage decreasing Logic input voltage Junction temperature Electrical Characteristics 6 V < VS < 18 V; IN1 = IN2 = HIGH IOUT1, 2 = 0 A (No load); - 40 C < Tj < 150 C; unless otherwise specified Parameter Symbol Limit Values min. Current Consumption Quiescent current typ. max. Unit Test Condition Symbol Limit Values min. max. V After VS rising above VUV ON Outputs in tristate condition - - Unit Remarks
VS
VUV ON 40
- 0.3 - 0.3
VUV ON V VUV OFF V
7 150 V C
VIN1, 2 Tj
- 0.3 - 40
IS
-
-
10
mA
IN1 = IN2 = LOW; VS = 13.2 V
Under Voltage Lockout UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis
VUV ON VUV OFF VUV HY
- 3.5 0.2
5 4.4 0.6
6 - -
V V V
VS increasing VS decreasing VUV ON - VUV OFF
Semiconductor Group
9
1998-02-01
TLE 5205-2
Electrical Characteristics (cont'd) 6 V < VS < 18 V; IN1 = IN2 = HIGH IOUT1, 2 = 0 A (No load); - 40 C < Tj < 150 C; unless otherwise specified Parameter Symbol Limit Values min. Outputs OUT1, 2 Static Drain-Source-On Resistance Source IOUT = - 3 A typ. max. Unit Test Condition
RDS ON H -
200 - 350 -
400 650 500 800 400 650 600
m m m m m m m
6 V < VS < 18 V Tj = 25 C 6 V < VS < 18 V
Sink
RDS ON L -
200 - 400 -
IOUT = 3 A
1000 m
VS ON < VS 6 V Tj = 25 C VS ON < VS 6 V 6 V < VS < 18 V Tj = 25 C 6 V < VS < 18 V VS ON < VS 6 V Tj = 25 C VS ON < VS 6 V
Note: Values of RDS ON for VS ON < VS 6 V are guaranteed by design.
Overcurrent Source shutdown trippoint Sink shutdown trippoint Shutdown delay time Short Circuit Source current Sink current - ISCH - - - - 20 15 A A - ISDH 6 6 25 9 9 50 - - 80 A A s - - -
ISDL tdSD
ISCL
t < tdSD t < tdSD
Semiconductor Group
10
1998-02-01
TLE 5205-2
Electrical Characteristics (cont'd) 6 V < VS < 18 V; IN1 = IN2 = HIGH IOUT1, 2 = 0 A (No load); - 40 C < Tj < 150 C; unless otherwise specified Parameter Symbol Limit Values min. Open Circuit Pull up resistor Pull down resistor Switching threshold H Switching threshold L typ. max. Unit Test Condition
RUP RDOWN VEH VEH
5 5 2 2
10 10 2.5 2.4
20 20 3.5 3.5
k k V V
- - - -
Output Delay Times (device active for t > 1 ms) Source ON Sink ON Source OFF Sink OFF
td ON H td ON L td OFF H td OFF L
- - - -
7.5 7.5 5 5
20 20 20 20
s s s s
IOUT = - 3 A
resistive load
IOUT = 3 A
resistive load
IOUT = - 3 A resistive load IOUT = 3 A resistive load
Output Switching Times (device active for t > 1 ms) Source ON Sink ON Source OFF Source OFF
tON H tON L tOFF H tOFF L
- - - -
15 5 2 2
30 10 10 10
s s s s
IOUT = - 3 A
resistive load
IOUT = 3 A
resistive load
IOUT = - 3 A
resistive load
IOUT = 3 A
resistive load
Semiconductor Group
11
1998-02-01
TLE 5205-2
Electrical Characteristics (cont'd) 6 V < VS < 18 V; IN1 = IN2 = HIGH IOUT1, 2 = 0 A (No load); - 40 C < Tj < 150 C; unless otherwise specified Parameter Symbol Limit Values min. Clamp Diodes Forward Voltage High-side Low-side Leakage Current Source Sink Logic Control Inputs IN 1, 2 H-input voltage threshold L-input voltage Hysteresis of input voltage H-input current L-input current Error Flag Output EF Low output voltage Leakage current Thermal Shutdown Thermal shutdown junction temperature typ. max. Unit Test Condition
VFH VFL
- -
1 1.1
1.5 1.5
V V
IF = 3 A IF = 3 A
ILKH ILKL
- 200 - - -
- 200
A A
OUT1 = VS OUT2 = GND
VINH VINL VINHY IINH IINL
2.8 - 0.4 -2 - 10
- - 0.8 - -4
- 1.2 1.2 2 0
V V V A A
- - -
VIN = 5 V VIN = 0 V
VEFL IEFL
- -
0.25 -
0.5 10
V A
IEF = 3 mA VEF = 7 V
TjSD
150
175
200
C
-
Semiconductor Group
12
1998-02-01
TLE 5205-2
Electrical Characteristics (cont'd) 6 V < VS < 18 V; IN1 = IN2 = HIGH IOUT1, 2 = 0 A (No load); - 40 C < Tj < 150 C; unless otherwise specified Parameter Thermal switch-on junction temperature Temperature hysteresis Symbol Limit Values min. typ. - 30 max. 170 - C K - - 120 - Unit Test Condition
TjSO
T
FU ; S
6 2 3 5 EF IN1 IN2 470 nF 1 4700 F 63 V
EF IN1
V EF
VS
OUT1
OUT1
R Load VS
TLE 5205-2
OUT2 GND 4 7
IN2
V IN1 V IN2
OUT2
V OUT1 V OUT2
FL
AES02396
Figure 4
Test Circuit Overcurrent Short Circuit Open Circuit
IOUT
ISD
ISC
IOC
Semiconductor Group
13
1998-02-01
TLE 5205-2
VIN
V 5 50% 0
_ t r = t f < 100 ns
t
OUT Source
A 3
t dONH
90% 50% 10%
t dOFFH
90% 50% 10%
0
t
OUT Sink
A 3
t ONH t OFFL
90% 50% 10%
t OFFH t ONL
90% 50% 10%
0
t dOFFL
t dONL
t
AET01994
Figure 5
Switching Time Definitions
+5V +V S 2 k 2 P 3 5 EF IN1 IN2 6 100 F 1 100 nF OUT2 GND 4
AES02397
VS
OUT1
TLE 5205-2
7
M
N =3A BL = 6 A
Figure 6
Application Circuit
Semiconductor Group
14
1998-02-01
TLE 5205-2
IN1, 2
SCH OUT1, 2 SDH
VOUT1, 2
R Short x SCH t dSD V FL
EF
AED01997
Figure 7
Timing Diagram for Output Shorted to Ground
IN1, 2
SCL OUT1, 2 SDL
VOUT1, 2
VS R Short x SCL t dSD V FU
EF
AED01998
Figure 8
Timing Diagram for Output Shorted to VS
Semiconductor Group
15
1998-02-01
TLE 5205-2
Diagrams Quiescent Current IS (active) versus Junction Temperature Tj
7
AED02398
Static Drain-Source ON-Resistance versus Junction Temperature Tj
0.6
AED02399
S
mA 6
R ON
0.5 Low Side Transistor
5
0.4
4
V S = 18 V
0.3
3
0.2
High Side Transistor
2
VS =6V
0.1
1 -50
0
50
100
C 150
0 -50
0
50
100
C 150
Tj
Tj
Input Switching Thresholds VINH, L versus Junction Temperature Tj
3.0
AED02400
Clamp Diode Forward Voltage VF versus Junction Temperature Tj
1.3
AED02401
V INH, L
2.5
V INH
VF
1.2 High Side Transistor
2.0
1.1
V INL
1.5
1.0
Low Side Transistor
1.0
0.9
0.5
0.8
0 -50
0
50
100
C 150
0.7 -50
0
50
100
C 150
Tj
Tj
Semiconductor Group
16
1998-02-01
TLE 5205-2
Overcurrent Shutdown Threshold ISD versus Junction Temperature Tj
12
AED02402
SD
10 Low Side Transistor 8 High Side Transistor
6
4
2
0 -50
0
50
100
C 150
Tj
Error-Flag Saturation Output Voltage VEF versus Junction Temperature Tj
0.6
AED02403
Switching Threshold VEH, VEH versus Junction Temperature Tj
3.0
AED02404
V EF
0.5
V EH ,V EL 2.8
0.4
2.6
V EH
0.3
2.4
0.2
2.2
V EL
0.1
2.0
0 -50
0
50
100 C 150 Tj
1.8 -50
0
50
100 C 150 Tj
Semiconductor Group
17
1998-02-01
TLE 5205-2
Package Outlines P-TO220-7-11 (Plastic Transistor Single Outline Package)
10 0.2 9.8 0.15 8.5 1) 3.7 -0.15 4.4 1.27 0.1
A
15.65 0.3
1)
17 0.3
2.8 0.2
13.4
0.05
8.6 0.3
10.2 0.3
C 0...0.15 1.27
3.70.3
9.25 0.2
0.5 0.1 3.9 0.4
7x 0.6 0.1 0.25
M
2.4 8.4 0.4
AC
1)
Typical All metal surfaces tin plated, except area of cut.
GPT09083
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Semiconductor Group 18
Dimensions in mm 1998-02-01
TLE 5205-2
P-DSO-20-10 (Plastic Dual Small Outline Package)
11 0.15 1) 2.8
3.5 max.
1.3
0.25 +0.0 7 -
1.2 -0.3
0 +0.15 3.25 0.1
B
0.02
15.74 0.1 1.27 0.4
+0.13
0.1 0.25
M
6.3 14.2 0.3
A 20x
Heatsink 0.95 0.15 0.25
M
20
11
Index Marking
1 1 x 45
10
A 1) Does not include plastic or metal protrusion of 0.15 max. per side
15.9 0.15 1)
GPS05791
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 19
Dimensions in mm 1998-02-01
5 3 B
TLE 5205-2
P-TO263-7-1 Option E3180 (Plastic Transistor Single Outline Package)
10 0.2 9.8 0.15 A
10.3
4.4 1.27 0.1 B 0.1 2.4
2.7 0.3
8.5 1)
0.05
9.25 0.2
(15)
8 1)
0...0.15 7x0.60.1 6x1.27
8 max.
4.7 0.5
0.5 0.1
0.25
1)
M
AB
0.1
GPT09114
Typical All metal surfaces tin plated, except area of cut.
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 20
Dimensions in mm 1998-02-01
TLE 5205-2
P-TO220-7-12 (Plastic Transistor Single Outline Package)
10 0.2 9.8 0.15 8.5 1) 3.7 -0.15 A B 4.4 1.27 0.1
170.3 15.65 0.3
1)
2.8 0.2
13.4
0.05
110.5
C 0...0.15 1.27
13 0.5
7x 0.6 0.1 0.25
M
0.5 0.1 2.4 ABC
1)
Typical All metal surfaces tin plated, except area of cut.
GPT09084
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Semiconductor Group 21
9.25 0.2
Dimensions in mm 1998-02-01

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